CLR_RXF=0, MDIS=0, SMPL_PT=00, DOZE=0, MTFE=0, FRZ=0, ROOE=0, DCONF=00, DIS_TXF=0, CONT_SCKE=0, PCSSE=0, DIS_RXF=0, PCSIS=0, CLR_TXF=0, MSTR=0, HALT=0
Module Configuration Register
| HALT | Halt 0 (0): Start transfers. 1 (1): Stop transfers. |
| SMPL_PT | Sample Point 0 (00): 0 protocol clock cycles between SCK edge and SIN sample 1 (01): 1 protocol clock cycle between SCK edge and SIN sample 2 (10): 2 protocol clock cycles between SCK edge and SIN sample |
| CLR_RXF | Flushes the RX FIFO 0 (0): Do not clear the RX FIFO counter. 1 (1): Clear the RX FIFO counter. |
| CLR_TXF | Clear TX FIFO 0 (0): Do not clear the TX FIFO counter. 1 (1): Clear the TX FIFO counter. |
| DIS_RXF | Disable Receive FIFO 0 (0): RX FIFO is enabled. 1 (1): RX FIFO is disabled. |
| DIS_TXF | Disable Transmit FIFO 0 (0): TX FIFO is enabled. 1 (1): TX FIFO is disabled. |
| MDIS | Module Disable 0 (0): Enables the module clocks. 1 (1): Allows external logic to disable the module clocks. |
| DOZE | Doze Enable 0 (0): Doze mode has no effect on the module. 1 (1): Doze mode disables the module. |
| PCSIS | Peripheral Chip Select x Inactive State 0 (0): The inactive state of PCSx is low. 1 (1): The inactive state of PCSx is high. |
| ROOE | Receive FIFO Overflow Overwrite Enable 0 (0): Incoming data is ignored. 1 (1): Incoming data is shifted into the shift register. |
| PCSSE | Peripheral Chip Select Strobe Enable 0 (0): PCS5/ PCSS is used as the Peripheral Chip Select[5] signal. 1 (1): PCS5/ PCSS is used as an active-low PCS Strobe signal. |
| MTFE | Modified Timing Format Enable 0 (0): Modified SPI transfer format disabled. 1 (1): Modified SPI transfer format enabled. |
| FRZ | Freeze 0 (0): Do not halt serial transfers in Debug mode. 1 (1): Halt serial transfers in Debug mode. |
| DCONF | SPI Configuration. 0 (00): SPI |
| CONT_SCKE | Continuous SCK Enable 0 (0): Continuous SCK disabled. 1 (1): Continuous SCK enabled. |
| MSTR | Master/Slave Mode Select 0 (0): Enables Slave mode 1 (1): Enables Master mode |